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I'm trying to generate a clean 11.289 MHz clock signal from the general-purpose clock, GPCLK0 on GPIO4. The suggested route is to use the 19.2 MHz crystal as the source, which seems to work for lower frequencies, but no matter what I try it defaults to 2.5 kHz. Reading the documentation, it seems to imply that the PLL sources should be used.

What further information is there on what the mentioned sources are? Particularly:

  • 4 = PLLA per
  • 5 = PLLC per
  • 6 = PLLD per

See page 107 - Clock Control Register of the BCM2835 Peripheral Documentation.

Peter Mortensen
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Dog Ears
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  • Did you solve the problem? I would like to generate too a clock signal (between 2-10 MHz), because i would like to read data from shift registers. But i can't make it work. How can i set up the GPCLK0 on GPIO4 pin for a clock signal output? Thanks! – user3171 Nov 05 '12 at 12:02

2 Answers2

8

I have done a bit of experimenting with the general purpose clocks.

This information appears to be correct (on the post date).

Refer to http://www.raspberrypi.org/wp-content/uploads/2012/02/BCM2835-ARM-Peripherals.pdf pages 102-108. The clock frequencies were determined by experiment. The oscillator (19.2 MHz) and PLLD (500 MHz) are unlikely to change.

Clock sources

0     0 Hz     Ground
1     19.2 MHz oscillator
2     0 Hz     testdebug0
3     0 Hz     testdebug1
4     0 Hz     PLLA
5     1000 MHz PLLC (changes with overclock settings)
6     500 MHz  PLLD
7     216 MHz  HDMI auxiliary
8-15  0 Hz     Ground

The integer divider may be 2-4095. The fractional divider may be 0-4095.

There is (probably) no 25MHz cap for using non-zero mash values.

There are three general purpose clocks.

The clocks are named GPCLK0, GPCLK1, and GPCLK2.

The clocks are accessible from the following gpios.

Don't use GPCLK1 (it's probably used for the Ethernet clock).

gpio4  GPCLK0 ALT0
gpio5  GPCLK1 ALT0 B+ and compute module only (reserved for system use)
gpio6  GPCLK2 ALT0 B+ and compute module only
gpio20 GPCLK0 ALT5 B+ and compute module only
gpio21 GPCLK1 ALT5 Not available on Rev.2 B (reserved for system use)

gpio32 GPCLK0 ALT0 Compute module only
gpio34 GPCLK0 ALT0 Compute module only
gpio42 GPCLK1 ALT0 Compute module only (reserved for system use)
gpio43 GPCLK2 ALT0 Compute module only
gpio44 GPCLK1 ALT0 Compute module only (reserved for system use)
joan
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5

Although it is not specified explicitly, I assumed from the spec that:

  • PLLA = 650 MHz
  • PLLB = 400 MHz
  • PLLC = 200 MHz

From this, I would suggest the following:

SRC = 4 (PLLA), MASH = 1, DIVI = 57, DIVF = 592

If I am reading the specs right, this will produce:

min freq = 11.207 MHz, max freq = 11.404 MHz, avg freq = 11.289 MHz

You can try MASH as 2 and 3 experimentally if those work better. You can also try the slower PLL clocks, although accuracy will probably slightly suffer. This is also mentioned in the documentation:

In applications where jitter is a concern, the fastest available clock source should be used.

Nakedible
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